Design and analysis of a novel fast adder using logical effort method

Addition, as one of the fundamental math operations, is applied widely in Very-large-scale integration systems and digital signal processing, such that computational speed a system depends mainly on its adders. There are various types adders based different methods. A novel adder proposed which performs addition path with fewer number levels, and, hence, higher lower power consumption. The goal innovation to design structured fast has block can be expanded bits, this design, calculation consumption circuit optimal. Each several formulae each level stated. designed multiplexers OR gates. performance been investigated evaluated two parts mathematical calculations simulation, it also compared other existing adders, ripple carry adder, skip select look ahead prefix kogge-stone cases 8, 16, 32 64 bits. results show collector good adders-based consumption, delay product area metrics.